1. Field
One or more embodiments described herein relate to a memory system.
2. Description of the Related Art
Efforts are continually being made to reduce the size and number of input/output pads of memory devices. At the same time, attempts are being made to increase capacity and operation speed in order to enhance performance.
Reducing the number of input/output pads of a memory device may involve decreasing the number of pads for receiving commands. The commands may include, for example, addresses. As memory capacity increases, the number of pads (e.g., address pads) may decrease, while the number of bits of the address may increase. Thus, commands may be transferred over a plurality of clock cycles.
When a command is transferred over a plurality of clock cycles, the time duration for transferring the command through a corresponding command pad may exceed the time duration for transferring data through data pads. This may cause inefficiencies or otherwise may disrupt performance.